`define reset               0
`define true                1
`define false               0

//PC (instruction address) related
`define PC_WIDTH	        32
`define NOP_PC		        32'hBFBFFFFC
//`define NOP_PC              32'hBFC00000

//Instruction related
`define INST_WIDTH		    32
`define NOP_INST		    {`INST_WIDTH{1'b0}}

//Register related
`define REG_ADDR_WIDTH		5
`define ZERO_REG_ADDR		5'b00000
`define REG_WIDTH			32
`define ZERO_REG			{`REG_WIDTH{1'b0}}


//ALU related
`define ALUOP_WIDTH			5
//ALUOP
`define ADD_ALU             5'b00001    // op1 + op2 (signed)
`define ADDU_ALU            5'b00010    // op1 + op2 (unsigned)
`define SUB_ALU             5'b00011    // op1 - op2 (signed)
`define SUBU_ALU            5'b00100    // op1 - op2 (unsigned)
`define LessThan_ALU        5'b00101    // if op1 < op2, then write 1, or write 0 (signed)
`define LessThanU_ALU       5'b00110    // if op1 < op2, then write 1, or write 0 (unsigned)
`define DIV_ALU             5'b00111    // op1 / op2 (signed)
`define DIVU_ALU            5'b01000    // op1 / op2 (unsigned)
`define MUL_ALU             5'b01001    // op1 * op2 (signed)
`define MULU_ALU            5'b01010    // op1 * op2 (unsigned)
`define AND_ALU             5'b01011    // op1 & op2
`define NOR_ALU             5'b01100    // op1 nor op2
`define OR_ALU              5'b01101    // op1 | op2
`define XOR_ALU             5'b01110    // op1 ^ op2
`define SLL_ALU             5'b01111    // op2 << op1 (logic)
`define SRA_ALU             5'b10000    // op2 >> op1 (ar)
`define SRL_ALU             5'b10001    // op2 >> op1 (logic)
`define LUI_ALU             5'b10010    // pass op1

//Div related
`define DIV_RUN				2'b00
`define DIV_AVA				2'b01
`define DIV_DONE			2'b10

// CP0
`define EXCCODE_WIDTH       5
`define Exc_None            5'h0f
`define Exc_PCAdEL          5'h14
`define Exc_Int             5'h00
`define Exc_AdEL            5'h04
`define Exc_AdES            5'h05
`define Exc_Sys             5'h08
`define Exc_Bp              5'h09
`define Exc_RI              5'h0a
`define Exc_Ov              5'h0c
`define Exc_ERET            5'h01